Goldman Sachs: threshold for quantum advantage in derivative pricing
Researchers from Goldman Sachs, University of Maryland and IBM Quantum give an upper bound on the resources required for valuable quantum advantage in pricing derivatives. To do so, they give the first complete resource estimates for useful quantum derivative pricing, using autocallable and Target Accrual Redemption Forward (TARF) derivatives as benchmark use cases.
They uncover blocking challenges in known approaches and introduce a new method for quantum derivative pricing – the re-parameterization method – that avoids them. This method combines pre-trained variational circuits with fault-tolerant quantum computing to dramatically reduce resource requirements. They find that the benchmark use cases examined require 7.5k logical qubits and a T-depth of 46 million and thus estimate that quantum advantage would require a logical clock speed of 10Mhz.
Although current estimates target logical clock rates around 10kHz (i.e. orders of magnitudes slower than our requirement), researchers are optimistic that future work on algorithms, circuit optimization, error correction, and hardware will continue to improve the required resource estimates and runtimes. For example, in the case of Shor’s algorithm, the estimated resource requirements have reduced by almost three orders of magnitude through careful analysis across several publications.
This work represents the first milestone on the journey towards quantum advantage for pricing financial derivatives. Researchers also emphasized that the resource estimation approach they presented can be fruitfully applied to analyze thresholds in other financially relevant applications: there are many potential areas for quantum advantage in finance where advantage thresholds would provide useful targets for both industry and the research community, which are summarized in two publications cited by the researchers here and here.
While the resource requirements given here are out of reach of current systems, researchers hope to provide a roadmap for further improvements in algorithms, implementations, and planned hardware architectures.
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